1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to an array substrate of a liquid crystal display device and a method of making an array substrate of a liquid crystal display device.
2. Discussion of the Related Art
In general, since flat panel display devices are thin, light weight, and have low power consumption, they are commonly used as displays of portable electronic devices. Among the various types of flat panel display devices, liquid crystal display (LCD) devices are commonly used for laptop computers and desktop computer monitors because of their superior resolution and their ability to produce high quality colored images.
Operation of the LCD devices makes use of optical anisotropy and polarization properties of liquid crystal molecules to generate a desired image. The liquid crystal molecules have a specific alignment due to their specific characteristics that can be modified by induced electric fields. For example, the electric fields induced to the liquid crystal molecules can change the alignment of the liquid crystal molecules, and due to the optical anisotropy of the liquid crystal molecules, incident light is refracted according to the alignment of the liquid crystal molecules.
The LCD devices include upper and lower substrates having electrodes that are spaced apart and face into each other, and a liquid crystal material is interposed therebetween. Accordingly, when the electric field is induced to the liquid crystal material through the electrodes of each substrate, an alignment direction of the liquid crystal molecules is changed in accordance with the applied voltage to display images. By controlling the induced voltage, the LCD device provides various light transmittances to display image data.
Among the different types of LCD devices, active matrix LCDs (AM-LCDs) having thin film transistors and pixel electrodes arranged in a matrix form provide high resolution images and superior moving images. A typical LCD panel has an upper substrate, a lower substrate, and a liquid crystal material layer interposed therebetween. The upper substrate, which is commonly referred to as a color filter substrate, includes a common electrode and color filters, and the lower substrate, which is commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFT's) and pixel electrodes.
FIG. 1 is an expanded perspective view of a liquid crystal display device according to the related art. In FIG. 1, an LCD device 11 includes an upper substrate 5, which is commonly referred to as a color filter substrate, and a lower substrate 22, which is commonly referred to as an array substrate, having a liquid crystal material layer 14 interposed therebetween. A black matrix 6 and a color filter layer 8 are formed in a shape of an array matrix on the upper substrate 5 that includes a plurality of red (R), green (G), and blue (B) color filters surrounded by the black matrix 6. In addition, a common electrode 18 is formed on the upper substrate 5 to cover the color filter layer 8 and the black matrix 6.
A plurality of thin film transistors T are formed in an array matrix corresponding to the color filter layer 8 on the lower substrate 22. A plurality of crossing gate lines 13 and data lines 15 are perpendicularly positioned such that each TFT T is located adjacent to each intersection of the gate lines 13 and the data lines 15. Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region p defined by the gate lines 13 and the data lines 15 of the lower substrate 22. The pixel electrode 17 includes a transparent conductive material having high transmissivity, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
In FIG. 1, a storage capacitor C is disposed to correspond to each pixel p and is connected in parallel to each pixel electrode 17. The storage capacitor C comprises a portion of the gate line 13, which functions as a first capacitor electrode, a storage metal layer 30, which functions as a second capacitor electrode, and an interposed insulator 16 (in FIG. 2). Since the storage metal layer 30 is connected to the pixel electrode 17 through a contact hole, the storage capacitor C electrically contacts the pixel electrode 17.
Accordingly, a scanning signal is supplied to a gate electrode of the thin film transistor T through the gate line 13, and a data signal is supplied to a source electrode of the thin film transistor T through the data line 15. As a result, liquid crystal molecules of the liquid crystal material layer 14 are aligned and arranged by enablement of the thin film transistor T, and incident light passing through the liquid crystal layer 14 is controlled to display an image. For example, the electric fields induced between the pixel and common electrodes 17 and 18 re-arrange the liquid crystal molecules of the liquid crystal material layer 14 so that the incident light can be controlled to display the desired images in accordance with the induced electric fields.
When fabricating the LCD device 11 of FIG. 1, the upper substrate 5 is aligned with and attached to the lower substrate 22. However, the upper substrate 5 may be misaligned with the lower substrate 22 and light leakage may occur due to a marginal error in attaching the upper and lower substrate 5 and 22.
FIG. 2 is a schematic cross-sectional view along II—II of FIG. 1 showing a pixel of a liquid crystal display device according to the related art. In FIG. 2, the LCD device includes the upper substrate 5, the lower substrate 22, and the liquid crystal layer 14. The upper and lower substrates 5 and 22 are spaced apart from each other and the liquid crystal layer 14 is interposed therebetween. The thin film transistor T is formed on the front surface of the lower substrate 22 and includes a gate electrode 32, an active layer 34, a source electrode 36, and a drain electrode 38. In addition, a gate insulation layer 16 is interposed between the gate electrode 32 and the active layer 34 to protect the gate electrode 32 and the gate line 13. As shown in FIG. 1, the gate electrode 32 extends from the gate line 13 and the source electrode 36 extends from the data line 15. The gate, source, and drain electrodes 32, 36, and 38 are formed of a metallic material while the active layer 34 is formed of silicon. Furthermore, a passivation layer 40 is formed on the thin film transistor T for protection. The pixel electrode 17 is formed of a transparent conductive material and is disposed on the passivation layer 40 while contacting the drain electrode 38 and the storage metal layer 30.
As previously described, the gate line 13 functions as a first electrode of the storage capacitor C and the storage metal layer 30 functions as a second electrode of the storage capacitor C. Thus, the gate electrode 13 and the storage metal layer 30 constitute the storage capacitor C with the interposed gate insulation layer 16.
In FIG. 2, the upper substrate 5 is spaced apart from the lower substrate 22 over the thin film transistor T. On a rear surface of the upper substrate 5, the black matrix 6 is disposed in positions corresponding to the thin film transistor T, the gate line 13, and the data line 15. For example, the black matrix 6 is formed along an entire surface of the upper substrate 5 and has openings corresponding to the pixel electrode 17 of the lower substrate 22, as shown in FIG. 1. The black matrix 6 prevents light leakage except for portions of the pixel electrode 17 and protects the thin film transistor T from the light, thus preventing generation of photo current in the thin film transistor T. The color filter layer 8 is formed on the rear surface of the upper substrate 5 to cover the black matrix 6 and includes red 8a, green 8b, and blue 8c colors filters, each corresponding to one pixel region p where the pixel electrode 17 is located. In addition, a common electrode 18 formed of a transparent conductive material is disposed on the color filter layer 8 over the upper substrate 5.
In FIG. 2, the pixel electrode 17 has a one-to-one correspondence with one of the color filters 8a, 8b, and 8c. Furthermore, in order to prevent a cross-talk between the pixel electrode 17 and the gate and data lines 13 and 15, the pixel electrode 17 is spaced apart from the data line 15 by a distance A and from the gate line 13 by a distance B. Accordingly, open spaces within the distances A and B between the pixel electrode 17 and the data and gate line 15 and 13 cause light leakage in the LCD device. For example, the light leakage mainly occurs within the open spaces A and B so that the black matrix 6 formed on the upper substrate 5 should cover those open spaces A and B. However, when arranging the upper substrate 5 with the lower substrate 22 or vice versa, a misalignment may occur between the upper substrate 5 and the lower substrate 22. Thus, the black matrix 6 is extended to fully cover those open spaces A and B to provide an aligning margin to prevent light leakage. However, by extending the black matrix, an aperture ratio of the liquid crystal panel is reduced as much as the aligning margin of the black matrix 6. Moreover, if there are errors in the aligning margin of the black matrix 6, the light leakage still occurs in the open spaces A and B, and deteriorates the image quality of the LCD device.
To overcome such disadvantages, an array substrate having a color filter-on-thin film transistor (COT) structure has been suggested.
FIG. 3 is a cross sectional view illustrating a known array substrate having a color filter-on-thin film transistor (COT) structure.
As shown in FIG. 3, a gate line 54 and a gate electrode 52 are disposed on a substrate 50. Then, a gate insulating layer 56 is formed on the substrate 50 to cover the gate line 54 and electrode 52. An active layer 58 and an ohmic contact layer 60 are disposed in series on the gate insulating layer 56, especially over the gate electrode 53. On the ohmic contact layer 60, formed are source and drain electrodes 62 and 64 that are spaced apart from each other across the gate electrode 52. Although not shown in FIG. 3, the gate electrode 52 extends from the gate line 54, and the source electrode 62 extends from a data line (not shown). A storage metal layer 68 having an island shape is formed on the gate insulating layer 56 and overlaps a portion of the gate line 54. Accordingly, a thin film transistor T having the gate electrode 52, the active layer 58, the ohmic contact layer 60, the source electrode 62 and the drain electrode 64 is complete. Furthermore, a storage capacitor CST including the storage metal 68, the portion of the gate line 54 and the interposed gate insulating layer 56 is complete. A passivation layer 70 is disposed on the gate insulating layer 56 to cover the thin film transistor T and the storage capacitor CST. The passivation layer 70 is formed of silicon nitride (SiNx) or silicon oxide (SiO2), and has contact holes exposing portions of the drain electrode 64 and the storage metal layer 68. A black matrix 72 is disposed on the passivation layer 70 to cover the data line (not shown), the gate line 54 except the portion overlapped by the storage metal layer 68, and the thin film transistor T except the portion of drain electrode 64. The black matrix 72 is formed by way of coating and developing black resin. A color filter layer 74 having red (R) 74a, green (G) 74b and blue (B) 74c colors is formed on the passivation layer 70 to cover the black matrix 72. The color filter layer 74 also has contact holes that expose the portions of the drain electrode 64 and storage metal layer 68. An overcoat layer 76 is formed over an entire surface of the substrate 50 to cover the color filter layer 74. The overcoat layer 76 also has contact holes that expose the portion of the drain electrode 64 and storage metal layer 68. A transparent pixel electrode 80 is formed on the overcoat layer 76 and contacts both the drain electrode 64 and the storage metal layer 68 through the contact holes.
In the array substrate having the COT structure, as shown in FIG. 3, since the overcoat layer 76 is disposed between the color filter layer 74 and the pixel electrode 80, the process of forming the contact hole through the overcoat layer 76 is required in order to electrically connect the pixel electrode 80 to the thin film transistor T and storage capacitor CST. Furthermore, when forming the contact holes, problems are encountered that raise the cost of production and lower the process yield.